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| 62 CY29962 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer Features * * * * * * 2.5V or 3.3V operation Output frequency up to 150MHz Supports PowerPC (R) and Pentium(R) processors 21 clock outputs: drive up to 42 clock lines LVPECL or LVCMOS/LVTTL clock input Output-to-output skew < 150 ps * * * * * * * Split 2.5V/3.3V outputs Spread-spectrum-compatible Glitch-free output clocks transitioning Output disable control Pin-compatible with MPC9600 Industrial temperature range: -40C to +85C 48-pin TQFP package Table 1. Frequency Table[1] SELA 0 1 QA VCO/2 VCO/4 SELB 0 1 QB VCO/2 VCO/4 SELC 0 1 QC VCO/2 VCO/4 FB_SEL 0 1 FB_OUT VCO/8 VCO/12 Block Diagram Pin Configuration FB_IN AVDD VDDA QA0 QA1 QA2 QA3 QA4 QA5 REF_SEL TCLK PECL_CLK PECL_CLK# FB_IN SELA PLL 0 1 REF FB 0 1 /2 /4 /8 /12 0 1 DQ 0 1 2 3 4 5 VSS T C LK PEC L_C LK PEC L_C LK# VD D R EF_SEL F B_SEL AVD D SELA SELB SELC VSSC 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSSA FB_O U T Q B0 Q B1 VD D B Q B2 Q B3 VSSB Q B4 Q B5 Q B6 VD D B B 0 1 DQ 6 0 1 2 3 4 5 C Y29962 SELB 13 14 15 16 17 18 19 20 21 22 23 24 QC6 QC5 QC4 QC3 QC2 QC1 QC0 OE# VDDC VDDC VSSC VSSB C 0 1 DQ 6 0 1 2 3 4 5 SELC OE# 0 1 6 FB DQ FB_OUT FB_SEL Note: 1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1) or 25 MHz to 50 MHz (FB_SEL = 0). Cypress Semiconductor Corporation Document #: 38-07364 Rev. *B * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 26, 2002 QA6 VSS A VDDA VSSA CY29962 Pin Description[2] Pin 3 4 2 Name PECL_CLK PECL_CLK# TCLK VDDA VDDB VDDC VDD O 9 10 11 7 47 6 14 SELA SELB SELC FB_SEL FB_IN REF_SEL OE# PWR I/O I, PD PECL clock input I, PU PECL clock input I, PD External reference/test clock input O O O Clock Outputs. See Table 1 for frequency selections. Clock Outputs. See Table 1 for frequency selections. Clock Outputs. See Table 1 for frequency selections. Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL; see Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. Frequency Select Inputs. These inputs select the divider ratio at QA(0:6) outputs. See Table 1. Frequency Select Inputs. These inputs select the divider ratio at QB(0:6) outputs. See Table 1. Frequency Select Inputs. These inputs select the divider ratio at QC(0:6) outputs. See Table 1. Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1. Reference Select Input. When HIGH, the PECL clock is selected. When LOW, TCLK is the reference clock. Description 38, 39, 40, 42, QA(6:0) 43, 45, 46 26, 27, 28, 30, QB(6:0) 31, 33, 34 15, 16, 18, 19, QC(6:0) 21, 22, 23 35 FB_OUT I, PU I, PU I, PU I, PU I, PD Feedback Clock Input. Connect to FB_OUT for accessing the PLL. I, PU Output Enable Input. When asserted LOW, enables all of the outputs. I, PD When pulled HIGH, disables to high impedance all of the outputs except FB_OUT. Power supply for Bank A clock buffers Power supply for Bank B clock buffers Power supply for Bank C clock buffers Power supply for core Power Supply for PLL. When AVDD is set LOW, PLL is bypassed. Common ground for Bank A Common ground for Bank B Common ground for Bank C Common ground 37, 44 25, 32 13, 20 5 8 36, 41 24, 29 12, 17 1, 48 VDDA VDDB VDDC VDD AVDD VSSA VSSB VSSC VSS Table 2. Function Table Control Pin REF_SEL AVDD OE# SELA SELB SELC FB_SEL TCLK PLL Bypass, outputs controlled by OE# Outputs Enabled Output Bank A at VCO/2 Output Bank B at VCO/2 Output Bank C at VCO/2 Feedback Output at VCO/8 0 PECL_CLK PLL power Outputs Disabled (except FB_OUT) Output Bank A at VCO/4 Output Bank B at VCO/4 Output Bank C at VCO/4 Feedback Output at VCO/12 1 Note: 2. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (< 0.2"). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Document #: 38-07364 Rev. *B Page 2 of 7 CY29962 Description The CY29962 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of seven outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 400 MHz. This allows a wide range of output frequencies up to 150 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL select inputs (see Table 1). The VCO frequency is then divided down to provide the required output frequencies. Zero Delay Buffer When used as a zero delay buffer, the CY29962 will likely be in a nested clock tree application. For these applications the CY29962 offers a low-voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The CY29962 can then lock onto the LVPECL reference and translate with near zero delay to low-skew outputs. By using one of the outputs as a feedback to the PLL, the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge, thus producing a near-zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock, the Tpd of the CY29962 is a function of the configuration used. Document #: 38-07364 Rev. *B Page 3 of 7 CY29962 Maximum Ratings[3] Maximum Input Voltage Relative to VSS: ............. VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD protection ............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current:..................................................20 mA Table 3. DC Parameters VDD = 2.5V 5%, TA = -40C to +85C Parameter VIL[4] VIH[4] VPP VCMR[5] IIL[6] IIH[6] VOL[7] VOH[7] IDD CIN Description Input LOW Voltage Input HIGH Voltage Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Input LOW Current (@ VIL = VSS) Input HIGH Current (@ VIH = VDD) Output LOW Voltage Output HIGH Voltage Quiescent Supply Current Input Pin Capacitance IOL = 15 mA IOH = -15 mA VDD and AVDD 1.8 10 4 13 Conditions Min. VSS 1.7 500 VDD - 1.4 Typ. Max. 0.7 VDD 1000 VDD - 0.6 -120 120 0.6 Unit V V mV V A A V V mA pF This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: VSS < (VIN or VOUT) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Table 4. DC Parameters VDD = 3.3V 5%, TA = -40C to +85C Parameter VIL[3] VIH[3] VPP VCMR IIL[6] IIH[6] VOL[7] VOH[7] IDD CIN [5] Description Input LOW Voltage Input HIGH Voltage Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Input LOW Current (@ VIL = VSS) Input HIGH Current (@ VIH = VDD) Output LOW Voltage Output HIGH Voltage Quiescent Supply Current Input Pin Capacitance Conditions Min. VSS 2.0 500 VDD - 1.4 Typ. Max. 0.8 VDD 1000 VDD - 0.6 -120 120 Unit V V mV V A A V V mA pF IOL = 24mA IOH = -24mA VDD and AVDD 2.4 15 4 0.55 20 Notes: 3. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. The LVCMOS inputs threshold is at 30% of VDD. 5. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within the VCMR range and the input lies within the VPP specification. 6. Inputs have pull-up/pull-down resistors that affect input current. 7. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Document #: 38-07364 Rev. *B Page 4 of 7 CY29962 Table 5. AC Parameters VDD = 3.3V 5% or 2.5V 5%, TA = -40C to +85C[8] Parameter Fref FrefDC Fvco Tlock Tr/Tf Fout FoutDC tpZL, tpZH tpLZ, tpHZ TCCJ Tskew Tskew Tskew(pp) Tpd Description Reference Input Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time Output Clocks Rise/Fall Time[9,10] Maximum Output Frequency Output Duty Cycle[9,10] Output Enable Time (all outputs) [9] Conditions FB_SEL = 1 FB_SEL = 0 Min. 16 25 25 200 Typ. Max. 33 50 75 400 10 Unit MHz % MHz ms ns MHz % ns ns ps 0.55V to 2.0V, VDD = 3.3V 0.5V to 1.8V, VDD=2.5V Q (/2) Q (/4) 0.1 100 50 45 2 2 100 50 1.0 150 100 55 10 8 Output Disable Time[9] (all outputs) Cycle-to-Cycle Jitter[9,10] Any Output to Any Output Skew[9,10] Bank to Bank Skew Part to Part Skew Phase Error[9,10] [11] Same Frequency Different Frequency Banks at different voltages 150 300 400 450 0 25 100 125 200 225 ps ps ps ps TCLK or PECL_CLK to FB_IN VDD = 3.3V VDD = 2.5V Notes: 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. 9. Outputs loaded with 30 pF each. 10. 50 transmission line terminated into VDD/2 11. Part-to-part skew at a given temperature and voltage. Ordering Information Part Number CY29962AI CY29962AIT Package Type 48-pin TQFP 48-pin TQFP - Tape and Reel Production Flow Industrial, -40C to +85C Industrial, -40C to +85C Document #: 38-07364 Rev. *B Page 5 of 7 CY29962 Package Drawing and 48-Lead Thin Plastic Quad Flat Pack (7x7x1.0 mm) A48A 51-85166-** PowerPC is a registered trademark of International Business Machines. Pentium is a registered trademark of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07364 Rev. *B Page 6 of 7 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29962 Document Title: CY29962 2.5V/3.3V, 150-MHz Multi-Output Zero Delay Buffer Document Number: 38-07364 REV. ** *A *B ECN NO. 112490 116092 122906 Issue Date 03/06/02 09/03/02 12/26/02 Orig. of Change CTK HWT RBI New Data Sheet Changed the Package Drawing and Dimension to CY standard on page 6. Add power up requirements to maximum ratings requirements Description of Change Document #: 38-07364 Rev. *B Page 7 of 7 |
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